Computer Organization and Design

Citation

Patterson, D. A., & Hennessy, J. L. (2017). Computer Organization and Design RISC-V Edition: The Hardware/Software Interface (1st ed.). Morgan Kaufmann.

Chapter Summary

This is the RISC-V Edition of the Patterson and Hennessy text (ISBN 978-0-12-812275-4), listed by Elsevier at 696 pages, with six chapters and four appendices. The publisher's description says the edition uses RISC-V, an open-source instruction set architecture designed for modern computing environments such as cloud computing, mobile devices and embedded systems. It adds that the book moves towards the post-PC era, with examples, exercises and material on mobile computing and the cloud, and updated content on tablets, cloud infrastructure and the x86 and ARM architectures. Advanced content, further appendices, a glossary, references and recommended reading are on an online companion site.

Chapter 1: Computer Abstractions and Technology

The opening chapter sets up the vocabulary of the field, in line with the book's subtitle, The Hardware/Software Interface: how a computer is described at several levels of abstraction and what technology underlies it.

Chapter 2: Instructions: Language of the Computer

The instruction set chapter. In this edition the instructions are those of RISC-V, the architecture the publisher singles out as the feature of the edition.

Chapter 3: Arithmetic for Computers

How a computer represents numbers and performs arithmetic in hardware.

Chapter 4: The RISC-V Processor

The processor chapter, named for the instruction set it implements; it covers the processor that implements the instruction set of Chapter 2.

Chapter 5: Large and Fast: Exploiting Memory Hierarchy

The memory-system chapter. The companion site refers to a Section 5.12 and provides a downloadable test case module with SystemVerilog code, which can be used to build a cache and cache controller in an FPGA.

Chapter 6: Parallel Processors from Client to Cloud

The final chapter moves from a single processor to parallel systems, in line with the publisher's emphasis on mobile and cloud computing.

Appendices A–D

Appendix A is The Basics of Logic Design; the others are Appendix B, Graphics and Computing GPUs; Appendix C, Mapping Control to Hardware; and Appendix D, A Survey of RISC Architectures for Desktop, Server, and Embedded Computers. The companion site lists Appendices B–D among its downloadable PDFs, together with the glossary, index and further reading organised by chapter.

Key Concepts

Chapters 1–3: the hardware/software interface

• Abstractions and technology: the topic named in Chapter 1's title, the starting point for the book's subtitle, The Hardware/Software Interface.
• Instruction set architecture: the contract between software and hardware; here RISC-V.
• Computer arithmetic: the subject of Chapter 3.

Chapters 4–6: implementation

• Processor datapath and control: the subject of Chapter 4, with the control-mapping topic of Appendix C.
• Memory hierarchy: the "large and fast" trade-off of Chapter 5, including caches.
• Parallel processors: Chapter 6's move from single processors to systems "from client to cloud".

Appendices

• Logic design: Appendix A, the digital-logic foundation for the processor chapters.
• GPUs and the RISC family: the topics of Appendices B and D.

Critical Analysis

Strengths

• One open instruction set throughout. The publisher presents RISC-V as the first open-source architecture designed for modern computing environments, so readers work with an instruction set that is documented openly rather than tied to one vendor.
• Logic background included. The contents place The Basics of Logic Design in Appendix A, so a reader who has not taken a separate digital-logic course has a starting point in the same volume; the other three appendices are on the companion site.
• Substantial companion material. The publisher's companion site offers historical perspectives and further reading for each chapter, advanced-content sections, a RISC-V reference data sheet (the "green card"), VHDL and Verilog tutorials, lecture slides, an errata sheet and the cache test case module. A hands-on component for FPGA-based work is therefore available.
• A clear intended audience. Elsevier gives the readership as undergraduates in computer science, computer engineering and electrical engineering, in courses from sophomore requirements to senior electives, as well as professional system designers and developers.

Limitations

• One architecture. Because the processor chapter is built on RISC-V, readers who want a worked implementation of MIPS or ARM need a different edition; Elsevier also publishes an ARM edition.
• Part of the material is online. Appendices B–D, the advanced-content sections and the historical perspectives sit on the companion site, so a reader with only the printed text gets a subset.
• Not the newest edition. Elsevier's page marks a newer edition as available (a second RISC-V edition exists), so page and section numbers in a course syllabus may differ from this one.

Where It Fits in the Course

Among the circuits and electronics books on the list, this is the only one about how a computer is organised rather than how circuits and devices behave. Agarwal and Lang's Foundations of Analog and Digital Electronic Circuits and Storey's Electronics: A Systems Approach both include digital material and are natural companions for the logic-level background; Howe and Sodini's Microelectronics: An Integrated Approach goes down to the devices from which processors are built.

Alexander and Sadiku's Fundamentals of Electric Circuits and Scherz and Monk's Practical Electronics for Inventors belong earlier or alongside, and Hayt and Buck's Engineering Electromagnetics is a separate field-theory strand. Patterson and Hennessy is best read after an introductory course in programming and digital logic, as the point where the circuit-level and software-level pictures are joined.

How to Use This Book

The book is intended for undergraduates in computer science, computer engineering and electrical engineering, and, in Elsevier's readership list, for professional system designers, programmers and developers. Some prior programming and a first look at logic gates make it easier; Appendix A fills in logic basics.

A practical plan:

• Core: Chapters 1 and 2 first, then Chapter 3 and Chapter 4 in order. Learn the RISC-V instruction set with the reference "green card" beside the text.
• Next: Chapter 5, and use the cache test case module if the course has FPGA access.
• Then: Chapter 6 for parallel systems; Appendix B if graphics processors are part of the course.
• Alongside: the Verilog or VHDL tutorials on the companion site if you plan to implement the datapath, and the chapter-by-chapter historical perspectives for context.