Computer Architecture: A Quantitative Approach

Citation

Hennessy, J. L., & Patterson, D. A. (2017). Computer Architecture: A Quantitative Approach (6th ed.). Morgan Kaufmann.

Chapter Summary

The sixth edition has seven chapters in print, followed by three review appendices (A to C); further reference appendices (D to M) are provided online. According to the publisher, every chapter has "Putting It All Together" sections near its end that apply the chapter's principles to real technology, and the edition has updated case studies and exercises. New in this edition are examples in the RISC-V instruction set, a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing.

Chapter 1: Fundamentals of Quantitative Design and Analysis

The opening chapter sets up the book's approach to evaluating design choices with measurements and quantitative reasoning, and is the foundation for the chapters that follow.

Chapter 2: Memory Hierarchy Design

Design of the memory hierarchy. The publisher mentions new material on stacked DRAM in this edition.

Chapter 3: Instruction-Level Parallelism and Its Exploitation

Instruction-level parallelism and the techniques by which processors exploit it.

Chapter 4: Data-Level Parallelism in Vector, SIMD, and GPU Architectures

Data-level parallelism across vector, SIMD and GPU architectures. The publisher notes data comparing a new NVIDIA Pascal GPU with an Intel Skylake CPU with AVX-512.

Chapter 5: Multiprocessors and Thread-Level Parallelism

Multiprocessors and thread-level parallelism; the publisher notes extensive additions on multicore architecture and organization.

Chapter 6: The Warehouse-Scale Computer

An updated chapter on warehouse-scale computing, including the first public information on Google's newest warehouse-scale computer.

Chapter 7: Domain Specific Architectures

A new chapter explaining why, in the publisher's account, domain-specific architectures are the way forward for performance and energy efficiency after the end of Moore's Law and Dennard scaling. It also publishes several industry domain-specific architectures for the first time.

Appendices A–C (print)

Appendix A covers instruction set principles, Appendix B reviews the memory hierarchy, and Appendix C covers pipelining, from basic to intermediate concepts.

Online Appendices D–M

Storage systems, embedded systems, interconnection networks, vector processors, hardware and software for VLIW and EPIC, large-scale multiprocessors and scientific applications, computer arithmetic, a survey of instruction set architectures, advanced concepts on address translation, and historical perspectives and references.

Key Concepts

Chapters 1–3: Quantitative design, memory and ILP

• Quantitative design: choosing among designs by measurement and analysis rather than intuition.
• Memory hierarchy: layering memories to balance capacity, speed and cost.
• Instruction-level parallelism: executing multiple instructions at once within a single instruction stream.

Chapters 4–5: Data-level and thread-level parallelism

• Vector, SIMD and GPU architectures: hardware for applying one operation to many data items.
• Multiprocessors and thread-level parallelism: parallelism across processors and threads.

Chapters 6–7: Large systems and specialisation

• Warehouse-scale computer: a data-center-sized machine treated as a single computer.
• Domain-specific architectures: hardware tailored to a class of problems when general-purpose gains are limited.

Critical Analysis

Strengths

• A consistent method. The title and the opening chapter commit the book to a quantitative approach to design evaluation, and "Putting It All Together" sections tie each chapter to real systems.
• Current topics. The sixth edition adds a chapter on domain-specific architectures, an updated chapter on warehouse-scale computing and RISC-V examples; the publisher also lists stacked DRAM, GPU-versus-CPU data and multicore additions.
• Review appendices in print, depth online. Instruction set principles, memory hierarchy review and pipelining are in the printed book, so readers can refresh basics, while further reference appendices D to M are provided online.
• Recognition. The publisher notes a 2019 Textbook Excellence Award (Texty) for this edition.

Limitations

• Graduate level. The publisher gives graduate students and professional architects as the readership; the book builds on prior computer organization and digital logic.
• Reference appendices are not in the print volume. Appendices D to M, including storage, interconnection networks and computer arithmetic, are online only.
• A newer edition exists. Elsevier's page notes that a newer edition is available, so readers should check which edition their course uses.

Where It Fits in the Course

Hennessy and Patterson is the graduate-level architecture text of this course. Petzold's Code is a narrative explanation of how computers work for general readers, and Nisan and Schocken's The Elements of Computing Systems has the reader build a computer from logic gates up; both are far gentler. Harris and Harris's Digital Design and Computer Architecture, RISC-V Edition builds from digital logic to a pipelined RISC-V processor and is the natural undergraduate preparation, using the same instruction set as this edition's examples. Bryant and O'Hallaron's Computer Systems: A Programmer's Perspective looks at the machine from the programmer's side. Shen and Lipasti's Modern Processor Design goes deeper into the microarchitecture of superscalar processors than Chapter 3 and Appendix C.

How to Use This Book

The book is for graduate students, professional architects and designers, and compiler or system software developers who already know computer organization and digital logic.

A practical plan:

• Core: Chapter 1, then Chapters 2 and 3, with Appendices B and C as refreshers when needed.
• Parallelism: Chapters 4 and 5 for data-level and thread-level parallelism.
• Systems and trends: Chapters 6 and 7 for warehouse-scale computers and domain-specific architectures.
• Online appendices: consult D to M for storage, embedded systems, interconnection networks and other reference topics.
• Practice: work the case studies and exercises with each chapter and read the "Putting It All Together" sections.